The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs.
A lithography exposing process forms a patterned photoresist layer for various patterning processes, such as etching or ion implantation. In a typical lithography process, a photosensitive layer (resist) is applied to a surface of a semiconductor substrate, and an image of features defining parts of the semiconductor device is provided on the layer by exposing the layer to a pattern of radiation. As semiconductor processes evolve to provide for smaller critical dimensions, and devices reduce in size and increase in complexity including number of layers, a way of accurately patterning the features is in order to improve the quality, reliability, and yield of the devices.
Although numerous improvements to perform the lithography exposing process have been invented, they have not been entirely satisfactory in all respects. Consequently, it would be desirable to provide a solution to improve the lithographic system so as to increase the production yield of the semiconductor wafers.